(a) Field of the Invention
The present invention generally relates to a voltage converting buffer circuit including a CMOS inverter for inverting input data signal and a flip-flop latch circuit for shifting the voltage level of the inverted data signal, and in particular, to a voltage converting buffer circuit capable of realizing high speed flip-flop action in the flip-flop latch circuit.
(b) Description of the Related Art
Voltage converting buffer circuits including a CMOS inverter for inverting input data signal and a flip-flop latch circuit for shifting the voltage level of the inverted data signal are used for converting input data signal supplied from outside to output an inverted data signal having a different potential level. Referring to FIG. 5 showing a conventional voltage converting buffer circuit, the buffer circuit includes an inverter section 1 and a level shifter flip-flop section 2. The inverter section 1 has a CMOS inverter which includes a p-channel MOS transistor M1 and an n-channel MOS transistor M2. The input node IN of the voltage converting buffer circuit is connected to the gates of the p-channel MOS transistor M1 and the n-channel MOS transistor M2. The source of the p-channel MOS transistor M1 is supplied with a power source voltage VCC1, and the source of the n-channel MOS transistor M2 is grounded. The drains of the p-channel MOS transistor M1 and the n-channel MOS transistor M2 are connected together, and the output of the inverter section 1 is supplied to the gate of an n-channel MOS transistor M4 in the level shifter flip-flop section 2. The input node IN of the voltage converting buffer circuit is also connected to an n-channel MOS transistor M6 in the level shifter flip-flop section 2.
The level shifter flip-flop section 2 has a flip-flop latch circuit including a p-channel MOS transistor M3, the n-channel MOS transistor M4, a p-channel MOS transistor M5, and the n-channel MOS transistor M6. A power source voltage VCC2 is supplied to the sources of the p-channel MOS transistors M3 and M5, separately from the power source voltage VCC1, and the gates of transistors M3 and M5 are connected with the drains of the n-channel MOS transistors M6 and M4, respectively.
The drains of the p-channel MOS transistor M3 and the n-channel MOS transistor M4 are connected together. The drains of the p-channel MOS transistor M5 and the n-channel MOS transistor M6 are connected together to the output node OUT of the voltage converting buffer circuit. The sources of the n-channel MOS transistors M4 and M6 are grounded.
When the input node IN is at a high level, the p-channel MOS transistor M1 is OFF and the n-channel MOS transistor M2 is ON, whereby the output of the inverter section 1 is maintained at a low level. Thus, the n-channel MOS transistors M4 and M6 are OFF and ON, respectively, and accordingly, the output node OUT is at a low level (0V).
When the input node IN is at a low level, the p-channel MOS transistor M1 is ON and the n-channel MOS transistor M2 is OFF, whereby the output of the inverter section 1 is maintained at a high level. Thus, the n-channel MOS transistors M4 and M6 are ON and OFF, respectively. Accordingly, the p-channel MOS transistor M5 is ON due to a low level of the gate thereof, and thus the output node OUT is at a high level.
As described above, the input data signal supplied through the input node IN is inverted by the inverter section 1 and the level of the inverted data signal is shifted according to the power source voltage VCC2 by the level shifter flip-flop section 2.
When a signal transition occurs at the input node IN from a low level to a high level, or a high level to a low level, flip-flop action occurs in the level shifter flip-flop section 2, thereby generating a signal transition at the output node OUT from a high level to a low level, or a low level to a high level.
In the voltage converting buffer circuit as described above, if driving capability of the p-channel MOS transistor and the n-channel MOS transistor in the level shifter flip-flop section 2 are equivalent (i.e. balanced), a long time interval is required for the flip-flop action in the level shifter flip-flop section 2, and sometimes the flip-flop action itself is not effected.
Therefore, in the design of the level shifter flip-flop section 2, unbalance is introduced in the driving capability between the p-channel MOS transistors and the n-channel MOS transistors. In the case of FIG. 5, the driving capability of the n-channel MOS transistors is designed to be larger than the driving capability of the p-channel MOS transistors in the level shifter flip-flop section 2.
More specifically, the driving capability of a MOS transistor generally depends on the source-drain current of the MOS transistor, and thus depends on the gate width and the gate length of the MOS transistor. A larger gate width provides a larger driving capability, whereas a larger gate length provides a smaller driving capability. In addition, the driving capability of an n-channel MOS transistor is generally larger than that of a p-channel MOS transistor if both the MOS transistors have equivalent gate widths. Thus, in order to obtain equivalent driving capabilities, the gate widths of the p-channel MOS transistors and the n-channel MOS transistors are set at approximately 2:1 (for example, 10 .mu.m and 5 .mu.m, respectively, for the gate widths). In the buffer circuit of FIG. 5, it is generally determined that the gate widths of the p-channel MOS transistors and the n-channel MOS transistors are set, for example, at 6 .mu.m and 5 .mu.m, respectively, to obtain a larger driving capability for the n-channel transistor.
In the above configuration, the driving capability of the n-channel MOS transistors M4 and M6 is larger than that of the p-channel MOS transistors M3 and M5, to obtain smooth and high speed data transition from a high level to a low level at the output node OUT, and ON current during the signal transition (or flip-flop action) from the high level to the low level is reduced.
In the buffer circuit of FIG. 5, however, the above unbalance in fact results in a slow data transition from a low level to a high level at the output node OUT of the level shifter flip-flop section 2 in the case of input data transition from a high level to a low level at the input node IN of the inverter section 1, as shown in FIG. 6. In addition, the transition itself at the output node OUT does not successfully occur in some cases.